Comparision of Different Logic style for High Performance Wave Pipeline Circuit

Abstract

High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications .Existing logic families cannot provide both of them simultaneously. We propose Double Pass Transistor Logic (DPL) which can be used as a universal logic to provide finest grain pipelining without affecting overall latency or increasing the area. It  does not require  any special process steps and hence, can be  realized  in  a  normal process  technology  as  against  the CPL proposed  by  Yano et  al  [2] which uses  threshold  voltage  adjustment  of  selected  devices.  The design procedure is described for (a) low latency, (b) high throughput and (c) low area requirements. In  addition to the various  advantages,  it  is envisioned  that DPL  designs  can also be used to build ultra-high speed  pipelined system without pipelining latches, viz., wave pipelined  digital systems,  where the throughput achievable  is beyond  that permitted  by  the delay  of  a pipeline stage.